The present invention relates to a mixed-type semiconductor integrated circuit device having bipolar transistors and MISFETs (Metal-Insulator-Semiconductor Field Effect Transistors) mounted on the same substrate, and particularly to a mixed-type semiconductor integrated circuit device using an SOI (Silicon On Insulator) structure of a type wherein bipolar transistors and MISFETs are formed in a semiconductor layer formed on a substrate with an insulating layer interposed therebetween.
A MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using an SOI structure has been disclosed in the article "IEDM" (International Electron Device Meeting), Tech. Dig. p683-686, 1991, for example.
A mixed-type semiconductor integrated circuit device using the SOI structure has been disclosed in, for example, Japanese Patent Application Laid-Open Publication No. 4-69966 (Application date: Jul. 10, 1990) filed by the applicant of the present application. In the disclosure, a silicon layer is formed on the surface of a semiconductor substrate with an insulating layer interposed therebetween. Further, bipolar transistors and MISFETs are formed in the silicon layer.
Each of the MISFETs has a source region, a channel forming region and a drain region respectively successively arranged in the silicon layer, and a gate electrode formed on the surface of the channel forming region with a gate insulating film interposed therebetween. In the mixed-type semiconductor integrated circuit device using the SOI structure, the source and drain regions of each MISFET are substantially covered with an insulator and the parasitic capacitance applied to each of the source and drain regions can be reduced. Since a circuit comprised of complementary MISFETs, for example, can provide high-speed charging and discharging rates upon activation of a circuit serving as the following stage, the mixed-type semiconductor integrated circuit device can be operated at high speed.
The silicon layer in which the channel forming region of the MISFET is fabricated, is formed with a film thickness selectively thinner than that of the silicon layer formed with the bipolar transistor, for example, a film thickness of 100 [nm] or less. As a result, the channel forming region of the MISFET can be completely depleted under the operation of the MISFET and hence a Kink characteristic can be avoided.
When, on the other hand, it is required to make the operating speed of each bipolar transistor faster, the bipolar transistor is fabricated in the form of a vertical structure and an npn type. The bipolar transistor extends in the direction of depth of the silicon layer from the surface thereof along the direction of the film thickness of the silicon layer and has respective operating regions corresponding to an n-type emitter region, a p-type base region and an n-type collector region, which are successively arranged in the silicon layer. The silicon layer formed with each bipolar transistor is formed with a film thickness selectively thicker than that of the silicon layer formed with each MISFET. As a result, the bipolar transistor can provide a reduction in resistance of the n-type collector region formed as a buried type in the silicon layer. Further, the cut-off frequency f.sub.T can be improved. Thus, the operating rate of the mixed-type semiconductor integrated circuit device can be made faster.
Further, all of element structures, pattern structures and manufacturing processes of the mixed-type semiconductor integrated circuit device can be used in common and simplified by applying the SOI structure to each bipolar transistor in a manner similar to the MISFET.